1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
As a technique for enhancing the mobility of a transistor, combined use of a so-called damascene gate electrode structure and a stress liner film that applies stress to the channel region of the transistor is being studied. The damascene gate electrode structure is obtained by forming a metal gate electrode inside a trench formed by removing a dummy gate with the intermediary of a gate insulating film having a high dielectric constant. In general, the stress liner film is formed of a single-layer film.
For example, as shown in FIG. 7A, element isolation regions 113 by which an element formation region 112 is isolated are formed on a semiconductor substrate 111, and then a dummy gate pattern 142 is formed above the element formation region 112 of the semiconductor substrate 111 with the intermediary of a dummy gate insulating film 141. The dummy gate pattern 142 is formed of a poly-silicon film, and a silicon nitride film may be formed thereon. The dummy gate insulating film 141 is formed of a silicon oxide film.
Lightly doped regions 131 and 132 are formed in the semiconductor substrate 111 on both the sides of the dummy gate pattern 142. The lightly doped regions 131 and 132 are referred to also as extension regions. A sidewall insulating film 121 is formed on the sidewall of the dummy gate pattern 142 above the lightly doped regions 131 and 132. This sidewall insulating film 121 is generally formed of a silicon nitride film.
Furthermore, in the semiconductor substrate 111 on both the sides of the dummy gate pattern 142, heavily doped regions 133 and 134 that have impurity concentration higher than that of the lightly doped regions 131 and 132 and serve as source and drain are formed with the intermediary of the lightly doped regions 131 and 132.
Metal silicide layers 135 and 136 are formed on the heavily doped regions 133 and 134.
In addition, a stress applying film 151 for applying stress to the channel region of the transistor is formed over the semiconductor substrate 111 in such a manner as to cover the dummy gate pattern 142, the sidewall insulating film 121, and so on. In general, this stress applying film 151 is formed by using a silicon nitride film having tensile stress for an N-channel metal oxide semiconductor (NMOS) transistor, and is formed by using a silicon nitride film having compressive stress for a P-channel metal oxide semiconductor (PMOS) transistor.
In such a state, chemical mechanical polishing (CMP) is performed to expose upper part of the part composed of poly-silicon, of the dummy gate pattern 142. After the poly-silicon of the dummy gate pattern 142 is exposed, this dummy gate pattern 142 composed of the poly-silicon is removed by e.g. etching. Moreover, the dummy gate insulating film 141 is removed by wet etching with use of a dilute hydrofluoric acid.
As a result, as shown in FIG. 7B, a gate electrode formation trench 123 is formed in the area from which the dummy gate pattern 142 (see FIG. 7A) and the dummy gate insulating film 141 (see FIG. 7A) are removed. At the time of the etch removal of the dummy gate insulating film 141, part of the stress applying film 151, which is formed of a silicon nitride film, in contact with and in the vicinity of the sidewall insulating film 121 is etched. The causes thereof include low film quality of the stress applying film 151 at the initial stage of film deposition thereof in a related-art method for forming the stress liner film. Specifically, insufficiency in the wet-etching resistance of the stress liner film obtained at the initial stage of the film deposition thereof will be a cause.
Due to the film thickness loss of the stress liner film accompanying the etching thereof, the degree of the stress application to the channel region by the stress applying film 151 is lowered, which causes a problem that sufficient stress can not be applied to the channel region. FIG. 8 shows an electron micrograph image of a section of the stress applying film 151 whose partial portion close to the sidewall insulating film 121 is etched (refer to e.g. S. Mayuzumi, J. Wang, M. Yamakawa, Y. Tateshita, T. Hirano, M. Nakata, S. Yamaguchi, Y. Yamamoto, Y. Miyanami, I. Oshiyama, K. Tanaka, K. Tai, K. Ogawa, K. Kugimiya, Y. Nagahama, Y. Hagimoto, R. Yamamoto, S. Kanda, K. Nagano, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima, “Damascene gate process wo mochiita top-cut dual stress liner wo yuusuru kouseinou Metal/High-k Gate MOSFET (High-performance Metal/High-k Gate MOSFET formed by using damascene gate process and having top-cut dual stress liner, in English)” “IEDM2007” special issue, the report of the 98-th workshop of Silicon Technology Division in the Japanese Society of Applied Physics, p. 22 to 25, edited and issued by Silicon Technology Division in the Japanese Society of Applied Physics, Jan. 24, 2008).